Advances in modern semiconductor fabrication technologies have impacted the computer industry and increased the demand for higher speed, lower cost, and higher density computer systems. Integrated circuit (IC) feature sizes have been reduced to approximately 1 micron, thereby facilitating an increase in the scale of circuit integration. Today, the function of a computer's central processing unit (CPU) can be implemented on a single IC chip, making possible computer systems that operate at high speeds. In order to maximize the benefit of such chip level capabilities, the performance of a memory subsystem must closely match that of the computer and, more specifically, that of the CFU.
The size and cost of the memory subsystem are major factors in the price/performance of the computer system. The maximum size of main memory is generally limited by the addressing capability of the CFU. With the development of high performance CPU chips, fast and large memory capabilities are required. However, modern random access memory devices or RAMs are relatively expensive and may constitute a large percentage of the total computer system size. Accordingly, high-density memory array packaging techniques are desired, particularly ones that can utilize older, less expensive memory chip technology without requiring redesign of existing computer platforms or cabinets. In some cases, high-density memory packaging may necessitate redesign of computer platform/cabinet elements such as the backplane, due to violation of spacing requirements, or the cooling system, due to an inability to remove heat from the high-density packages.
Another requirement of main memory is a high speed interconnection between the RAMS within the main storage subsystem and the CPU chips, since such off-chip interconnection is a limiting factor in realizing overall system performance. Memory devices, in general, are bus-oriented, thus making the interconnection between main memory and the CPU less complex and less prone to error. Nevertheless, the interchip interconnection strategy of the RAMs must minimize the contribution of added inductances and stray capacitances, so as to avoid decreasing memory subsystem performance.
Therefore, in accordance with an aspect of the present invention, a feature is to provide a new and improved method and apparatus for high-density memory array packaging which results in a larger and more economical memory subsystem.
Additionally a feature of the present invention is to provide a low-profile, thermally managed, high-density memory array package such that the memory array package may be inserted into a standard computer backplane without the need for redesign of the backplane or computer cooling system due to violation of spacing requirements or cooling specifications.
In accordance with another aspect of the present invention, a feature is to provide a high-density multichip module interconnecting memory chips on a multilayer interconnect member to a circuit board, thereby increasing the performance and density of the memory subsystem.
A further feature of the present invention is to provide a new and improved method and apparatus for high-density memory array packaging that integrates less complex, higher yielding and less expensive RAM devices on an interconnect member.